A 0.089mm 2 Multiply-Delay Locked Loop with Low Phase Noise and Uniform Phase Separation Based on Time Amplifier (TA) for TDC Applications

A low phase noise Multiply-Delay Locked Loop (MDLL) with uniform distribution multiple output clock phases is proposed in this paper. An auto-configured time amplifier (ACTA) with high gain is embedded in the phase frequency detector to reduce the static phase offset (SPO) and output phase noise. Additionally, a multiplexer (MUX) with dynamic load matching is adopted to achieve more precise clock injection. Test results indicate that the MDLL implemented by the TSMC 0.18[Formula: see text] [Formula: see text]m 1.8[Formula: see text]V standard CMOS process can successfully boost the frequency of the output clock to 500[Formula: see text]MHz with an input reference frequency of 25[Formula: see text]MHz, where the phase separation of the 4 clocks is locked around ([Formula: see text])[Formula: see text]. The phase noise at a 1[Formula: see text]MHz frequency offset is [Formula: see text]117.3[Formula: see text]dBc/Hz, the integrated RMS value of random jitter is about 2.28[Formula: see text]ps, the core area is approximately 0.089[Formula: see text]mm 2 and the core power is 5.886[Formula: see text]mW, suitable for TDC applications.