Power-Up Stable DC Offset Cancellation in CMOS Low-Pass Filters Using Mirrored Subthreshold Resistors

This paper presents a three-stage, fifth-order Butterworth active-RC low-pass filter integrated with a power-up stable CMOS DC offset cancellation (DCOC) circuit. The filter achieves a 120[Formula: see text]MHz cutoff frequency with a 4-bit programmable gain from 0 to 18[Formula: see text]dB. The DCOC circuit, implemented in the final stage, employs mirrored subthreshold resistor-based common-mode feedback sensing to minimize loading on high-impedance nodes. Power-up stability is enhanced by gain-stage-specific enable control. Designed and simulated in the ST 130[Formula: see text]nm PD SOI CMOS process, the circuit operates at 1.2[Formula: see text]V with an additional 1.8[Formula: see text]V supply for the DCOC. The design reduces the 3-[Formula: see text] output offset voltage from 200[Formula: see text]mV to 1.2[Formula: see text]mV at maximum gain, with a start-up settling time of 50[Formula: see text] [Formula: see text]s. The offset cancellation introduces lower cutoff frequencies of 46[Formula: see text]kHz and 11.3[Formula: see text]kHz at maximum and minimum gains, respectively. Total power consumption is 21[Formula: see text]mW, with an active area of about [Formula: see text]. The proposed filter demonstrates effective offset cancellation and reliable power-up stability, making it well-suited for high-performance programmable gain applications.