Practicality of MAGIC NOR in a 1T1M Crossbar Array For In-Memory Computing

Memristors offer a solution to the processor-memory bottleneck in traditional computer systems, particularly in storage systems with in-memory computing (IMC) capabilities. However, challenges such as stability and parameter variations hinder their widespread use. The MAGIC NOR gate has shown promise in memristive-based digital IMC architectures, but the presence of sneak paths in 0-Transistor 1-Memristor (0T1M) crossbars limits their effectiveness. The 1-Transistor 1-Memristor (1T1M) structure emerges as a practical solution to this issue. This paper evaluates the feasibility of using the MAGIC NOR gate in a 1T1M crossbar array for IMC and discusses the constraints of such a setup. Our analysis suggests that only row-wise or column-wise MAGIC NOR gate evaluation is practical for a 1T1M crossbar array, as opposed to a 0T1M array where both row-wise and column-wise gate evaluations are possible. We propose a scalable sneak-path-free 1T1M crossbar array with the MAGIC design style for IMC architecture, operating in resistive memory mode for data storage and IMC mode for logic operations. We also propose a novel heuristic mapping method that exploits parallelism across the crossbar array. Using the Cadence Spectre environment, simulation results on adder circuits and ISCAS-85 benchmark functions show that, on average, our proposed method achieves a 32.41% improvement in computation steps and saves more than 52.48% of memristor cells compared to other 0T1M MAGIC families.