Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution

This paper presents Gatling-V, an FPGA-optimized implementation of the RISC-V Vector extension that concurrently executes up to four vector instructions. The main innovation is using a multi-banked ASIC approach to build a vector register file from simple dual-port (1R1W) BRAMs rather than using traditional FPGA-based multi-port techniques. This saves both logic and BRAM, improves clock speed, and supports multiple overlapping in-flight instructions as well as vector chaining. However, it is limited to launching one vector instruction every two cycles. Using this technique, we build a RISC-V vector core that runs at 500MHz on AMD UltraScale+ HBM (16nm) with a 4R4W/8R8W register file and 2/4 fully parallel ALUs that use chaining (convoying) to reach peak utilization on sequentially dependent (independent) instructions with vectors longer than 36/72 (4/8) elements of 64b words, respectively. On microbenchmarks, the 4-ALU implementation is over 6 times faster than Saturn-V, an FPGA-optimized RISC-V vector engine, while consuming only twice as many LUTs but similar BRAMs and DSPs.