Finding and Understanding Bugs in FPGA Place-and-Route Engines
Abstract
Place-and-route (P&R) engines are a crucial part of the FPGA design flow, responsible for mapping a given netlist onto the physical resources of an FPGA device. It is critical that they work correctly, because they run after most verification activities have completed, and because their opaque machinations produce complicated outputs that defy manual inspection. However, we know of no prior work that scrutinises the correctness of P&R engines directly.
Fields of Study & Subjects
Physical Unclonable Functions (PUFs) and Hardware Security
Radiation Effects in Electronics
Formal Methods in Verification
Publication details
- Journal / source
- Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
- Publisher
- ACM
- Pages
- 23–33
- Publication date
- 5 February 2026