Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds

Excessive FPGA compilation times, often measured in hours, stifle rapid iterative development, design-space exploration, and runtime reconfiguration applications. Coarse-grain divide-and-conquer techniques, which break large applications into separately compiled pages, offer moderate speedups, potentially bringing compilation down to minutes, but leave significant fine-grain parallelism opportunities untapped. Systolic-array-based accelerators have previously offered orders of magnitude speedup for FPGA placement (a major bottleneck in compilation), by exploiting massive fine-grain parallelism, however poor scalability restricts them to small designs, and lack of support for modern heterogeneous netlists (CLBs, BRAMs, DSPs) prevents their use today. We introduce an enhanced, FPGA-based systolic placement accelerator, capable of placing divide-and-conquer page-sized netlists of CLBs, BRAMs, and DSPs onto VTR architectures, with 2-3 orders of magnitude speedup over VTR-9 running on a modern workstation-class processor. We demonstrate page-placement in milliseconds on realistic benchmarks, including HLS dataflow designs, run on an AMD Versal VCK190 implementation of our systolic placer, forging a path towards real-time, self-hosted FPGA compilation.