Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS

Circuits generated by dynamically scheduled high-level synthesis (HLS) outperform static counterparts when execution-dependent operation reordering is possible. A key opportunity are potential memory dependencies that static analysis cannot rule out: Statically scheduled circuits must assume a worst-case scenario, enforcing conservative in-order execution even when unnecessary. In contrast, dynamically scheduled circuits use load-store queues (LSQs) to detect access collisions at runtime and reorder accesses whenever possible. While effective, LSQs are costly in both area and timing due to their size and critical path. We argue that LSQs in application-specific circuits are overly generic, checking all ordering relationships instead of only the necessary ones. Instead of relying on LSQs, our approach generates dataflow circuits that enforce only essential dependencies, reducing resource usage while preserving execution time. We implemented our methodology in an open-source, state-of-the-art dynamic HLS compiler and compared it against optimized LSQs. Our solution exploits the same reordering opportunities to achieve consistently Pareto-optimal solutions in terms of wall-clock time and resources. On average, we obtain similar execution times (2% better) while reducing resources by 37%, offering a superior alternative for high-performance dataflow circuit synthesis. CCS Concepts • Hardware → High-level and register-transfer level synthesis; Reconfigurable logic applications.