Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators

Creating dataflow circuits with HLS tools to exploit memory- or task-level parallelism is challenging. These tools can generate functional designs easily, but optimizing them for performance often requires extensive code restructuring, pragma tuning, and even RTL integration. Writing low-level RTL, however, is rarely productive. We propose Chext, a domain-specific language that provides a thin abstraction layer over RTL for building complex dataflow circuits with elastic interfaces. Chext enables a safe and agile development flow with its novel approach and offers a rich component library to accelerate design, making such circuits more accessible on FPGAs. In this paper, we introduce Chext, outline its design principles, and present two case studies comparing it with Vitis HLS.