Multi-Port Memory with Bidirectional Ports for FPGAs Using XOR and LVT Methods

We propose a generalization to a previous XOR memory implementation to allow for any number of full, read-only, and write-only ports. This implementation creates these additional ports by encoding and decoding the data entries with XOR logic. The incoming (written) data is encoded with the data corresponding to the other ports and the outgoing (read) data is decoded by XORing all the entries in the memory banks. Using XOR operators to accomplish this encoding/decoding has advantages over other approaches because the XOR operator is a simple and efficient operation. The result is a high-throughput multi-ported memory that is particularly well-suited for implementation on FPGAs. We also implemented an efficient architecture for creating a live value table (LVT) memory using an XOR-based scheme by utilizing its bidirectional capabilities. We use an XOR memory with full ports to implement a bidirectional live value table design. We evaluate the architecture's performance and resource utilization, and show that the XOR-based bidirectional live value table is a compelling alternative for applications requiring high-performance, flexible memory access.