Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures (FPGAs) for Edge and Physical AI

Model Recovery (MR) builds physics-guided digital twins from data but runs inefficiently on GPUs due to iterative ODE solvers and memory-bound kernels. We introduce ModEl Recovery IN fpgabased Dynamic Architecture (MERINDA), based on replacing ODE solver with a GRU-based streaming dataflow and co-designs fixedpoint compute and on-chip memory (BRAM tiling, heterogeneous DSP/LUT mapping). On representative MR workloads, MERINDA yields up to 6.3× fewer cycles and 99.3% lower energy than an LTC-based FPGA baseline, enabling real-time edge deployment.