Modulation Recognition in a System-on-Chip

We present the development of specialized accelerator intellectual property for modulation recognition (MR) systems in edge artificial intelligence hardware optimized for low latency and power. Using high-level synthesis (HLS) for machine learning algorithms and manual register-transfer level (RTL) coding for signal processing tasks like the Strip Spectral Correlation Algorithm (SSCA), we integrated heterogeneous accelerators into a system-on-chip (SoC) environment using the Embedded Scalable Platforms (ESP) framework. The Field-Programmable Gate Array (FPGA) based dual accelerator design, consisting of both residual network (ResNet) and SSCA accelerators, demonstrated performance gains of more than 8x compared to software implementations on conventional hardware. Power savings was roughly a factor of 1.35x.