Closing the Loop on FPGA Verification: An Iterative Framework for Maximizing Routing Resource Coverage

Pre-silicon verification of Field-Programmable Gate Array (FPGA) architectures and their supporting Computer-Aided Design (CAD) tools presents a significant challenge. While static benchmark suites fail to provide adequate coverage of the vast routing fabric, the application of formal verification is computationally not practical at the scale of modern FPGAs. To address this, we present an automated, iterative framework designed to systematically maximize routing resource graph (rr_graph) coverage. Our methodology employs a three-level, coarse-to-fine-grained heuristic engine that generates placement constraints and designs to strategically target all resources aiming for 100% coverage, while supporting user-defined exclusions. In the first level, the engine prioritizes coarse-grained logic resource coverage by targeting uncovered grid locations with diverse micro-benchmarks. In the second level, it maximizes interconnect utilization by forcing routing-intensive designs into identified routing coldspots. Finally, in the third level, it performs fine-grained targeting of the remaining hard-to-reach routing resources by generating specialized micro-designs with precise locking and stretching constraints. This approach not only provides a robust methodology for verifying FPGA fabrics and CAD tool correctness but also enables the quantitative analysis of FPGA architectures, systematically identifying unreachable or inefficiently designed resources and providing actionable feedback to architects before tape-out.