Towards Scheduling of Pipelined Dataflow Graphs in MLIR

ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) 2026

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Authors: Gabriel Rodriguez‐Canal, Nícolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown
DOI: 10.1145/3748173.3779568
Cited by: 0
References: 1

Abstract

We present an MLIR flow that partitions neural networks and schedules them as software-driven macro-dataflow pipelines for low-latency streaming on CPU–FPGA SoCs. A new dataflow dialect and token-based scheduler pipeline even cyclic graphs with external memory, overcoming HLS limits. On an AlphaData ADM-PA101 (Versal VM1802) we demonstrate low-latency streaming; to our knowledge this is the first HLS flow to pipeline cyclic NN graphs.

Fields of Study & Subjects

Embedded Systems Design Techniques Parallel Computing and Optimization Techniques VLSI and FPGA Design Techniques

Publication details

Journal / source
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
Pages
138–138
Publication date
5 February 2026