Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture
Abstract
We address the area overhead of synthesizable eFPGAs by proposing the ''PAE Cell,'' an AIG-based multi-output logic cell, and a domain-specific routing architecture for control logic. Evaluations demonstrate that the PAE Cell achieves 4-LUT equivalence at approximately 0.4× the area, while our routing architecture reduces total eFPGA area by up to 80% compared to conventional islandstyle designs.
Fields of Study & Subjects
VLSI and FPGA Design Techniques
Embedded Systems Design Techniques
Physical Unclonable Functions (PUFs) and Hardware Security
Publication details
- Journal / source
- ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)
- Pages
- 181–181
- Publication date
- 5 February 2026