ETOF: An Efficient Transistor-Level Optimization Flow for Large-Scale CMOS Circuits

The computing efficiency of digital VLSIs has increased with advancements in manufacturing, but this progress is slowing due to post-Moore physical limits. To improve efficiency, better standard cell-level synthesis can reduce transistor counts for low-power design. However, the design space at this level is limited, leaving room for transistor-level optimization. While previous research has explored transistor-level optimization, most focus on small-scale circuits, and few large-scale approaches are coarse-grained and lack a global perspective. In this article, we propose an efficient transistor-level optimization flow for CMOS VLSIs. It includes (1) a partition algorithm with a fast quality estimation method based on a metric named weighted cell sharing rate, (2) a neural network model with dedicated feature selection to provide an accurate optimization potential evaluation, and (3) an effective iterative partition selection method with global consideration of the partitions’ dependencies, for obtaining partitions suitable for transistor-level synthesis tools. This flow can optimize a given digital circuit’s netlist for reducing the transistor count. The experimental results demonstrate that the proposed flow achieves an average reduction of 11.04% and 7.94% in transistor counts compared to standard cell logic synthesis and the advanced large-scale transistor-level optimization work, respectively.