Implications of Supporting Compressed Instructions in Area-Optimized Bit-Serial RISC-V Cores

Bit-serial RISC-V cores cover a distinctive corner in the design space, making them particularly interesting for highly area-constrained, ultra-low-cost applications in the IoT and extreme edge computing, such as smart sensors or single-use healthcare devices. Given their stringent focus on area demand, each feature must be carefully considered. One is the use of RISC-V compressed instructions by the RVC extension to reduce the memory footprint and, consequently, costs. While compressed instructions reduce the required ROM size by 22.4% on average in the Embench suite, the RVC extension is costly in terms of hardware resources. This work proposes three RVC implementations for the bit-serial FazyRV core and provides an in-depth analysis of their implications. We utilize open-source tools wherever applicable and base our evaluations on the iCE40, ECP5, GateMate, and 7-Series FPGA architectures, as well as estimates for an IHP-SG13G2 ASIC implementation. Our findings highlight the hardware cost of supporting compressed instructions in bit-serial cores, which increases the implementation size by 14.5% to 58% in a 1-bit FazyRV variant. Ultimately, none of the proposed RVC implementations is optimal for all targets. Thus, we provide guidance on decisions to be made in conjunction with the target architecture, the intended system performance, and the firmware.