SEC-CiM+: Selective and Reconfigurable Error Compensation for ReRAM-based Compute-in-Memory

ReRAM-based Compute-in-Memory (CiM) architectures provide a promising solution for accelerating Deep Neural Network (DNN) inference in edge computing environments. However, these architectures are susceptible to stuck-at-faults (SAFs), including stuck-at intermediate states, which degrade inference accuracy. To address this challenge, we propose a reconfigurable error compensation (EC) mechanism that selectively mitigates errors while operating under memory constraints. By leveraging an indexed storage format, our approach efficiently compensates for errors without excessive overhead. We develop a theoretical framework to determine the minimum number of critical columns requiring compensation and analyze how EC transitions between three modes of operation across different models. The EC mechanism requires only 0.3874 mW of additional power for single operational-unit correction and introduces negligible latency overhead, while sustaining near-baseline accuracy for DenseNet121, VGG16, ResNet18, and SwinT under high fault densities (5–10%). Moreover, the overall energy overhead remains below 6% for ResNet18 and VGG16, and below 10% for DenseNet121.