Assessment of Pocket Inside Junctionless Hybrid Double Gate Transistor for Low Power Circuit Applications

A Si 1-x Ge x pocket is reported to enhanced device performance, providing a boost in the proposed device on-current by 24.19%. The effects of adding a dual-k spacer (low-k + High-k) on the design viability of a pocket hybrid double gate junctionless transistor (PHDG-J n LT) were also examined. Compared to a traditional DG-J n LT, fringing field effects and off-current are reduced, enhancing energy band profiles. The suggested gadget is hence ideal for high-performance complimentary metal oxide semiconductor circuits. To enhance device performance, we also investigated optimisation of a suggested PHDG-J n LT structure. Near the source-channel interface, integrating a pocket close to the interface induces a local minimum in the conduction band edge. Both tunnelling speeds and current handling capacity are enhanced. To improve important device characterisation metrics such as on-state current (I on ), on-to-off-state current ratio (I on /I off ), subthreshold swing (SS), etc, the simulation study focused on optimising the position of the pocket. The resulting optimised design has a pocket length of 10 nm and a shift in pocket of 1 nm (5%) to 10 nm(50%) for a 20 nm channel length. A notable 20% to 59% boost in on current is achieved by this arrangement in the range of 0.7 mA μm −1 to 0.85 mA μm −1 compared to a standard HDG-J n LT.