Design and implementation of a novel approximate carry look ahead adder for low-power FIR filter applications

Approximate computing is a low-power circuit design strategy that trades off computational accuracy for gains in speed, power efficiency, and area reduction. This approach achieves considerable power and area efficiency by introducing acceptable errors. The acceptable error in computation systems refers to a loss in accuracy that does not affect overall system performance. Approximate computing is mainly suitable for multimedia and signal processing applications. In this work, a novel approximate carry look-ahead adder (CLA) based on logical level modification is proposed. The new carry prediction term is derived to reduce the overall propagation delay of the addition operation. The proposed multi-bit adder design uses a square root based division method to partition the adder stages. Moreover, the proposed adder is applied in finite impulse response (FIR) filter implementation to evaluate the performance in real-time applications. The proposed adder and FIR filter are coded in Verilog and verified using the Xilinx simulator. The result shows that the proposed FIR filter achieves better results in terms of all parameters.