Energy-efficient FinFET-based SRAM design for sustainable high-speed communication in next-generation IoT and IoBNT devices

The rapid growth of sustainable, next-generation wireless technologies such as 5G, IoT, IoBNT, and wearable biomedical systems demands energy-efficient hardware capable of high-speed data transmission with minimal power consumption. Static random-access memory (SRAM), a key component in these systems, faces challenges in power-sensitive applications due to leakage currents and read stability issues, especially in conventional 6T designs. This work presents a FinFET-based intramural loop 7T (IL7T) SRAM architecture optimized for ultra-low-power, high-speed performance. Leveraging 18nm FinFET technology, the IL7T design effectively reduces leakage power, improves stability, and enhances overall energy efficiency. Simulations in Cadence Virtuoso demonstrate significant reductions in power dissipation compared to traditional SRAM architectures, making it a promising solution for sustainable IoT edge nodes, implantable devices, and IoBNT applications where long-term operation and power conservation are critical.