DTGDI-based low-power Vedic multiplier using 16nm GNRFET

There is a higher demand for devices that have better energy efficiency and higher performance in the modern-day technological world, which are necessary for media processing applications. It must handle the intensive computational loads with minimal hardware. With this, the battery life can also be extended when it is used in the constrained environment. Multiplication becomes one of the important steps in those applications, so the usage of multipliers is unavoidable. Numerous digital multipliers exist, but Vedic multipliers enable the design of efficient devices. In this work, the Vedic multiplier is designed using GNRFET 16nm technology. The work also compares the static CMOS-based Vedic multiplier with designs based on Gate-Diffusion Input (GDI), modified GDI (mGDI), Dynamic Thresh-old MOSFET (DTMOS), and Dynamic Threshold GDI (DTGDI) techniques. The designs were analyzed using the Synopsys HSPICE EDA tool. The designed Vedic multiplier can be beneficial when we use it for low-frequency applications. Vedic multipliers based on DTGDI have a Power-Delay-Product (PDP) reduction of 36.16% for the ripple carry adder and 56.58% for the carry skip adder.