Design of parallel hardware architecture for feed-forward neural network and implementation using FPGA

This paper presents a parallel feed-forward neural network (PFFNN) architecture optimized for real-time inference on field programmable gate array (FPGA) platforms, validated using the Iris dataset. A 4 × 8 × 3 × 3 configuration was trained using MATLAB with 98.66% accuracy, and its parameters were quantized for hardware deployment. The architecture was synthesized on a Zedboard (xc7z020clg484–1) and evaluated in terms of timing performance and hardware resource utilization. Inference timing shows a significant speedup on hardware, executing in just 0.3 µs compared to 0.867 ms in software. The implementation uses minimal resources thus making it efficient for constrained environments. A comparative analysis with prior works demonstrates that the proposed architecture offers superior trade-offs between speed and resource usage, confirming its potential for low-power, real-time AI applications.