Compute-capable block RAMs for efficient deep learning acceleration on FPGAs

Field-programmable gate arrays (FPGAs) have evolved into powerful heterogeneous systems with high computational capabilities and distributed on-chip memory, making them a key platform for accelerating data-intensive applications. Modern FPGAs integrate large arrays of block RAMs (BRAMs), providing significant potential for optimizing memory-bound workloads. Reconfigurable in-memory accelerator (RIMA), is an efficient architecture that enhances traditional BRAMs with computational capabilities, enabling arithmetic operations directly within memory. RIMA leverages FPGA reconfigurability and compute-capable BRAMs featuring in-memory compute units called memory dot product engines (M-DPEs) and logic dot product engines (L-DPEs) to accelerate recurrent neural network (RNN) workloads. RIMA improves resource utilization and performance across various RNN models by allowing a customizable balance between in-BRAM and DSP-based computation. Additionally, by loading computation inside the memory, the number of clock cycle increases in the L-DPE. To overcome above bottleneck, this work proposes novel architecture by integrating the Radix 2 multiplier design in the accelerator to boost the performance of the design by reducing the clock cycles. Implemented and evaluated on Xilinx Vivado, RIMA achieves 248 logic units, 324 registers, 3 DSP blocks, a total thermal power dissipation of 532.37 mW and number of clock cycles reduced from 11 to 9 demonstrating its efficiency and potential in deep learning acceleration.