Design and implementation of efficient approximate multiplier with optimized compressor selection for nonlinear RGB image brightness adjustment

Multiplication is a critical operation in digital circuits, influencing the performance of arithmetic and signal processing applications. Approximate computing techniques, particularly in compressor-based multipliers, offer a balance struck between computational precision and resource utilization. This work investigates the impact of four different compressor designs (4:2, 5:2, 8:2) on an 8 × 8 multiplier, evaluating their area, power, and delay characteristics. Error analysis is conducted to assess the trade-offs between computational efficiency and accuracy. The best-performing compressor-based multiplier is then integrated into an image processing application, non-linear brightness adjustment of an RGB image, where the Red and Green channels undergo transformation while the Blue channel remains unaltered. The proposed design is implemented in Verilog and synthesized using Xilinx Vivado 2018.3. Results demonstrate that the selected multiplier achieves an optimal balance between performance and accuracy, making it suitable for error-resilient applications.