Optimizing FPGA-based data communication: performance evaluation of hybrid network-on-chip architecture for low latency and high throughput

In the evolving landscape of multiprocessor systems-on-chip (MPSoCs), achieving efficient, high-speed, and lowlatency data communication remains a critical design challenge, especially as system complexity increases with the integration of diverse processing cores and high-bandwidth applications. This study proposes an optimized FPGA-based data communication framework employing a hybrid network-on-chip (NoC) architecture tailored for low latency and enhanced throughput. The research introduces a robust network gateway system featuring integrated deserializers, serializers, temporary registers, electronic crossbar switches, and four gateway cores, effectively managing synchronized data flow between on-chip and off-chip networks. The proposed system incorporates a 2D mesh NoC topology with virtual routing techniques, combining wormhole and virtual cut-through switching, supported by FIFO-based buffering and FSM-controlled input channels to improve data routing efficiency. To further optimize system performance, a novel transition-based encoding and decoding mechanism is embedded within the NoC routers, reducing unnecessary bit transitions and thereby minimizing dynamic power dissipation. Comprehensive hardware resource utilization and power analysis were conducted on an Artix-7 FPGA platform, demonstrating significant reductions in resource usage and power consumption when compared to conventional architectures. Specifically, the proposed design achieved noticeable improvements in flip-flop and LUT utilization, while preserving BRAM efficiency and drastically lowering power consumption. This work offers a scalable, resource-efficient, and power-optimized communication strategy suitable for high-performance computing, realtime embedded applications, and future heterogeneous MPSoCs.