VLSI and Random S-box Based IoT Security by Variable Irreducible Polynomial GF (2) in Composite Field Arithmetic

The Internet of Things (IoT) describes a future where millions of objects and individuals are networked to transfer large volumes of data from multiple places. There are concerns about the privacy of data during the IoT’s transit phases. Therefore, this chapter proposes a security method that addresses the aforementioned challenges in order to enhance trustable data exchange, specifically during distribution between an IoT and cloud-based gateway employing proposed methodology and takes less execution time compared to traditional advanced encryption standard (AES), which is suitable for IoT environment. Here the algebraic and statistical robustness of the suggested S-boxes is examined. The hardware purpose of this study is to enhance the very large scale integration (VLSI) design 56 of the modified S-box and inverse S-box processes for the next generation of S-Boxes in composite field arithmetic. When compared to other encryption algorithms, the recommended AES design reduces the amount of time in clock-cycles required for encryption of 128 bits of information is 116 clock cycles, and the critical path delay drops from 7.49 to 6.28 ns (AES iterative design) and 6.59 ns (AES pipeline design), respectively. Therefore, the time required to finish the S-box, the AES transformation, and the AES pipeline for 128 bits of data is 2003.32, 728.48, and 764.4 ns, respectively. This is useful for IoT environment for low power comsumption. Using a hybrid suggested S-box and inverse S-box, where nine different irreducible polynomial and key are transmitted to the cloud server, can further increase the security performance. To use a brute-force attack and decrypt the proposed random S-Box 128-bit AES key would take 1.6328450984067 × 10 17 years.