Scheduling techniques in high-speed packet switches

Packet switches are at the heart of modern communication networks.Initially deployed for local-and wide-area computer networking, they are now being used in different contexts, such as interconnection networks for High-Performance Computing (HPC), Storage Area Networks (SANs) and Systemson-Chip (SoC) communication.Each application domain, however, has particular requirements in terms of bandwidth, latency, scalability and delivery guarantee.These requirements must be carefully taken into account and have a major impact on the design of the switch.We propose novel scheduling techniques that enable the construction of distributed (multi-chip) schedulers for large crossbars, develop a scheme for integrated scheduling of unicast and multicast traffic and study flow-control mechanisms that allow switches to achieve lossless behavior while providing fine-grained control of active flows.We also present a comparison between synchronous and asyncronous systems showing that asynchronous switching seems a competitive solution with respect to the more traditional synchronous approach.