Low-loss silica-SOI monolithically integrated single-mode waveguides via the fabrication of complementary etching-oxidation of silicon

In this work, we realize a large-size single-mode silica-on-silicon (SOS) waveguide from a small-size single-mode silicon-on-insulator (SOI) waveguide at the two ends of the chip by a phosphorous-dopant enhanced complementary etching-oxidation of silicon (CEOS) method to implement a low-loss fiber-chip butt-coupling (FCBC). We model and investigate the geometrical change, and P-dopant caused refractive index change of P:SiO 2 waveguide core with both the numerical calculation and software simulator. As a result, the SOS waveguide not only greatly reduces the FCBC loss but also creates the supersmooth sidewalls of waveguides. With such a CEOS technique, a large-sized single-mode SOS waveguide is fabricated to monolithically integrate with the SOI waveguide via a taper. Consequently, a ∼6 dB IL reduction and a ∼3 dB FCBC loss reduction are achieved, and then FCBC loss lower than 1.2 dB is predicted once the taper structure is optimized by a conformal transportation theory. Hence, this work is an alternative route to fabricating silicon photonic integrated circuit (PIC) chips that possess both the on-chip and FCBC optical losses.