Stacked III-V membrane diodes laterally grown on double-layer SOI for 3D Si photonics

Three-dimensional (3D) photonic integrated circuits (PICs) are poised to overcome the density and scalability limitations in conventional 2D architecture. However, limited by the low index contrast of III-V epi-layers and resultant micrometer-thick vertical diode structures, existing 3D platforms can only incorporate a single layer of III-V active devices. Here, we overcome this fundamental challenge via selective lateral heteroepitaxy on a double-layer silicon-on-insulator (DLSOI) wafer, demonstrating the monolithic integration of two stacked layers of III-V active photonic devices. The fabricated membrane diodes exhibit clear rectification, and the function of photodetection is experimentally demonstrated at the 1550 nm band. Combined with in situ doping and an embedded tunnel junction, our method features a simplified fabrication process, requiring only one epitaxy, one metallization, and no III-V etching. Our work establishes a scalable path toward seamlessly integrating multilayer III-V active components in future 3D Si photonics.