Implementation of neural networks on FPGAs with memristors for optimizing data processing in ATLAS

The High Luminosity LHC (HL-LHC) upgrade $($see $\text{Aberle~ O.}$ $et~ al.$, CERN-2020-010 (2020) https//doi.org/10.23731/CYRM-2020-0010$)$ will increase the instantaneous luminosity of the LHC by an order of magnitude, posing new challenges for the $\text{ATLAS}$ $(\text{ATLAS~ Collaboration}$, $JINST$, $\mathbf{3}$ (2008) S08003$)$ trigger and data acquisition systems. To cope with elevated particle flux and background, the ATLAS muon spectrometer is undergoing major Phase-II upgrades $(\text{Gazis~ Evangelos~ N.}$, $Symmetry$, $\mathbf{16}$ (2024) 1035$)$, including new detector layers and a redesigned Level-0 (L0) trigger architecture capable of running advanced algorithms on FPGAs. Among the key algorithmic developments is muon momentum regression at the trigger level, aimed at reducing false triggers from low-$p_T$ muons. The primary focus of this work is on the exploration of hardware technologies that can accelerate such inference tasks. In particular, we investigate the use of memristors $(\text{Chua~ L.}$, $IEEE~Trans.~Circuit~Theory$, $\mathbf{18}$ (1971) 507$)$ as analog, in-memory computing elements capable of performing highly parallel matrix-vector operations with extreme energy efficiency. We outline the principles and potential advantages of memristor-based acceleration in the context of trigger-level inference and present a conceptual integration into the ATLAS DAQ architecture. Finally, we report experimental results using Knowm self-directed channel memristors $(\text{Campbell~ Kristy~ A.}$, $Microelectron.~ J.$, $\mathbf{59}$ (2017) 10$)$, demonstrating the ability to iteratively program their conductance to target values with a few-percent precision, a critical requirement for storing neural network weights reliably. These findings support the feasibility of hybrid analog-digital architectures for future trigger systems in high-energy physics.