ASIC Design of Low Area RSA Crypto-core based on Montgomery Multiplier

Background/Objectives: Currently, the most popular public key encryption is RSA. We present a low area hardware design of RSA crypto-core based on the Montgomery algorithm in ASIC. Methods: We employed Carry Save Adder in the design of the multiplier which plays a critical role in the overall design. The proposed hardware was designed at Register Transfer Level using Verilog description language with Xilinx 14.3 ISE design suite and simulated with ModelSim. In ASIC implementation, TSMC 90nm and 130nm CMOS technology was employed for synthesis of the Montgomery multiplier and modular exponentiation respectively. Findings: The primal operation of RSA cryptosystem is modular exponentiation, computed by repetitions of modular multiplications. Fast modular multiplication algorithms over the years have been proposed to speed up exponentiation and yet maximize performance. The core of this paper evolved from the modification of the modified Montgomery multiplication algorithm. From the new algorithm, a hardware architecture which simplifies the operation of the Q_logic coupled with a compact two-level CSA in the Montgomery multiplier is designed. The simplified Q_logic design and the elimination of traditional BRFA and bypass circuitry accounted for a reduction in area. Furthermore, the new multiplier is applied in the H-algorithm to develop the modular exponentiation unit. Other relevant modules in the RSA crypto-core including the pseudorandom number generator, primality tester and key generator have been optimized for resource sharing to balance and improve speed and area of the system. Synthesis results of the proposed multiplier and exponentiation unit achieved a gate count of 60K and 79K representing a reduction of 47% and 28% respectively. Improvement/Applications: Our system is suitable for low area RSA applications. Future works on this paper will examine the analysis and design of Carry Save Adder to improve propagation delay.