Design of a ring oscillator for direct conversion of capacitance into frequency in capacitive sensor interfaces

This study examines CMOS ring oscillators that are used as converters of capacitive sensor parameters. The issue with most analytical models is their assumption of symmetric stage loading, making them inaccurate for the topology where a sensor connection to a single node introduces asymmetry. The lack of a validated model for 45-nm technology complicates the design of sensitivity and energy efficiency. An analytical model for the capacity to frequency converter that accounts for asymmetric loading has been built and verified. The model is based on the physical principle of summing asymmetric stage delays and a linear approximation of inverter delay versus load capacitance. A parametric analysis was performed in LTspice (sensor capacitance Csensor is from 0 to 2.5 pF) to verify the model. It was determined that the oscillation period has a quasi-linear dependence on capacitance; therefore, the frequency dependence is hyperbolic. The proposed model predicts the frequency with a maximum relative error of no more than 1.55% over the entire simulation range (21.17–29.96 MHz) compared to SPICE data. Key metrics have been analyzed: the average sensitivity is 3.52 MHz/pF, while the instantaneous sensitivity is non-linear, decreasing from 5.57 MHz/pF to 2.15 MHz/pF. Power consumption increases slightly (151.3–155.7 µW), as the capacitance growth is compensated by the frequency drop. Energy per cycle (Ecycle), conversely, increases almost linearly (5.05–7.35 pJ) with a slope of 0.92 pJ/pF. This closely matches the theoretical value of VDD2 = 1.0 pJ/pF, confirming the dominance of dynamic power consumption. The proposed model allows engineers to accurately predict and design the capacity-to-frequency characteristics, sensitivity, as well as power consumption of compact integrated sensor interfaces.