An enhanced time delay neural network technique for modeling of power transistors with self-heating effect

Accurate modeling of self-heating effect in power transistors is crucial for reliable design and performance evaluation of wireless communication circuits and systems. This letter presents an enhanced time delay neural network (TDNN) technique specifically developed to model power transistors considering self-heating effect. At first, an enhanced TDNN model topology suitable for power transistors is proposed. To accurately describe the self-heating effect, a thermal sub-circuit is incorporated into the model framework. Moreover, novel formulations for direct current, small-signal S-parameters, and large-signal harmonic balance outputs of the proposed TDNN are derived so that typical measurement data can be utilized for model training. Finally, training algorithm is also proposed to effectively optimize the weighting and thermal parameters in the proposed TDNN model. The effectiveness of the proposed technique is validated through a modeling example involving a practical power transistor. The resulting TDNN model is embedded in Keysight Advanced Design System, and simulation results based on this model demonstrate good agreement with the measured data.