Implementing low-performance-overhead logic locking in SoCs via homomorphic feedback

In Systems-on-Chips (SoCs), logic locking is a vital technique for protecting Intellectual Property (IP) cores from leakage. Existing logic locking schemes based on Homomorphic Encryption (HE) employ a serial-blocking architecture, embedding high-latency cryptographic modules into the processor’s data path. This approach incurs significant performance overhead and limits the achievable security level. To address this bottleneck, this paper presents Homomorphic Feedback Locking (HFL), an architecture that decouples HE operations from the CPU’s execution path into a parallel, non-blocking feedback loop accessed via Control and Status Registers. We implemented HFL in a RISC-V SoC, characterized the privilege escalation event intervals under a system call workload, and developed a queuing model to analyze its performance overhead. Experimental results show that HFL with 83-bit security incurs a System Call performance overhead of only 15.0%, an improvement over the 33.5% overhead of a 41-bit serial-blocking scheme. Our model predicts performance scaling, explaining the overhead as a function of cryptographic workload and event arrival rate.