Hierarchical reverse model for automated analog integrated circuit sizing

This work presents HiTAN, a hierarchical reverse modeling framework for automated analog IC sizing. Unlike conventional forward modeling, HiTAN directly infers design parameters from target performance specifications through an automated simulation-preprocessing pipeline combined with a lightweight multi-task attention mechanism. Validation on two representative LDO topologies demonstrates that HiTAN achieves high prediction accuracy, with an average parameter error below 2% and overall performance prediction accuracy exceeding 97%. Compared with baseline models, HiTAN consistently reduces design errors by a significant margin and generates parameter sets that satisfy multi-dimensional performance constraints, thereby enhancing circuit stability, efficiency, and robustness. These results confirm that reverse modeling not only accelerates the analog design process by reducing simulation overhead but also improves design quality and scalability for complex analog IC tasks.