Efficient finite field inversion using parallel Hex-ITA framework on FPGA

Finite field inversion is a fundamental operation in cryptographic systems, particularly in Elliptic Curve Cryptography (ECC). The Itoh-Tsujii Algorithm (ITA) is a prevalent method for efficient inversion in hardware implementations within binary extension fields. This paper introduces an optimized parallel architecture for ITA that reduces computation time by minimizing clock cycles while maintaining a balanced trade-off in delay and area utilization. Our approach leverages a Hex-ITA framework in GF(2233), integrating Hex and Hex-root operations in parallel to enhance efficiency. The proposed design achieves a new benchmark in performance over existing designs. Experimental findings validate the scalability and performance of the proposed architecture, establishing it as a reliable choice for ECC-based cryptographic solutions.