A 0.2-20 GHz ultra-low noise amplifier using parasitic-conscious optimization techniques
Abstract
In this letter, a 0.2-20 GHz ultra-wideband low-noise amplifier is proposed and fabricated using a 0.15-μm E-mode GaAs pHEMT process. To achieve high performance across ultra-wide bandwidths, we innovatively propose a design methodology that systematically integrates parasitic parameters as core design variables. Based on the methodology, a negative feedback topology along with an ultra-wideband decoupling network is designed and have been implemented. The fabricated chip exhibits a gain of 15.6 dB across the 0.2-20 GHz range with a gain ripple of ±0.6 dB and a noise figure below 1.86 dB. S11 and S22 are better than -12 dB and -8 dB, respectively. The proposed LNA also achieves an OP1dB of 17 dBm and an IP1dB of 1.4 dBm under a power consumption of 400 mW. Additionally, the fabricated LNA occupies a chip area of only 1.5 × 1.0 mm2, including all pads.
Fields of Study & Subjects
Radio Frequency Integrated Circuit Design
Microwave Engineering and Waveguides
Superconducting and THz Device Technology
Publication details
- Journal / source
- IEICE Electronics Express
- Publisher
- Institute of Electronics, Information and Communications Engineers (IEICE)
- Volume
- 23
- Issue
- 8
- Pages
- 20260037–20260037
- Publication date
- 5 February 2026
- Language
- EN