An asymmetric transformer-based Doherty power amplifier in 65-nm CMOS

In this letter, a 38 GHz asymmetric Doherty power amplifier (PA) that utilizes common-source (CS) amplifiers with different gate widths for the main and auxiliary PAs to align their optimal load impedances. Both the input quadrature hybrid network (QHN), output power combiner and inter stage matching network are designed by transformer-based structure. Furthermore, a quarter-wavelength impedance inverter is integrated into the output power combiner using a π-type C-L-C network, resulting in a more compact topology. The proposed Doherty PA, implemented in 65-nm CMOS process with a compact core area of 0.6×0.42 mm2. At 38 GHz, the measured saturated output power (Psat), 1-dB output compression point (OP1dB) and peak power added efficiency (PAE) are 19.7 dBm, 19.2 dBm and 25.4 %, respectively. The measured PAE at 6-dB power back-off (PBO) is 19.1 %.