Ultra-high throughput implementation of 5G new radio low-density parity-check encoder for ASIC and FPGA

To address the limitations in flexibility and universality of existing 5G NR QC-LDPC encoders, this paper proposes a novel and unified high-throughput encoder architecture. The proposed design supports all base graphs and lifting factors, and is implementable on both FPGA and ASIC platforms. It features dedicated parallel circuits for computing λ and p2 for both base graphs, respectively, alongside a custom-optimized circuit for computing p1. A pipeline design that overlaps computation with output effectively hides input processing latency, ensuring computational units remain nearly continuously active. After the initial delay for the first code block, the output almost delivers data at a rate of twice the Zc width per clock cycle. Synthesis results demonstrate peak throughputs of 459.13 Gbps (information) / 960 Gbps (parity) on ASIC and 78.97 Gbps (information) / 165.12 Gbps (parity) on FPGA, representing exceptionally high performance on their respective platforms. Furthermore, the architecture achieves remarkable block-to-block latencies of merely 18.4 ns on ASIC and 107 ns on FPGA—critical metrics for latency-sensitive communication applications.