Analysis of Device Parameters on Steep Subthreshold Slope Gate-Controlled Carrier-Injection Silicon-on-Insulator Transistor

In this study, we investigated the device parameters of a gate-controlled carrier-injection silicon-on-insulator transistor (GCCI SOI-Tr) capable of achieving a steep subthreshold slope of less than 1 mV/dec. Six device parameters: base impurity concentration (Nb), base length (Lb), channel impurity concentration (Nch), gate length, gate width, and argon implantation were varied. GCCI SOI-Tr has a unique structure with an inherent p-n-p-n thyristor and a connection between a p-channel metal-oxide semiconductor field effect transistor (MOSFET) and a lateral bipolar junction transistor (BJT) using a dummy gate. Accordingly, the dependence of the GCCI SOI-Tr characteristics on device parameters exhibited similarities to those of MOSFET and BJT. In particular, the amplification capability was increased by a lower Nb and shorter Lb, and the trigger voltage was controlled by Nch. This indicates that the optimization of the GCCI SOI-Tr is possible by separating the optimization of the MOSFET and BJT components using a method similar to that of the conventional transistor.