Design and Implementation of a Digital Coherence BPSK Demodulator using FPGA
Abstract
JIn this paper, we propose the design and implementation mechanism for a digital coherence BPSK demodulator based on the use of Direct Digital Frequency Synthesizer (DDFS) and digital filter using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1.The proposed demodulator has the following parameters: =50MHz.CLK Clock frequency: F -/ K=50000 KHz /1250 =40 KHz ).CLK = F sam : (f KHz = 40 sam -Frequency range: (3
Fields of Study & Subjects
Embedded Systems and FPGA Applications
Advancements in PLL and VCO Technologies
Digital Filter Design and Implementation
Publication details
- Journal / source
- IMRJR
- Volume
- 3
- Issue
- 3
- Publication date
- 9 March 2026
- Language
- EN