Advanced Hardware Security on Embedded Processors: A Systematic Review Protocol (2020-2026)

SYSTEMATIC REVIEW PROTOCOL REGISTRATION Title: Advanced Hardware Security on Embedded Processors: A 2026 Review Authors: Ali Kia, Aaron W. Storey, Masudul H. Imtiaz Affiliation: Clarkson University, Potsdam, NY, USA RETROSPECTIVE REGISTRATION NOTICE: This protocol was registered after the systematic search and data extraction were completed. The registration documents the methodology as implemented, in accordance with PRISMA 2020 guidelines for retrospective registration disclosure. 1. OBJECTIVES This systematic review examines hardware-level security developments for microcontroller-class devices from 2020-2026, covering five domains: Post-Quantum Cryptography (PQC), Physical Unclonable Functions (PUF), Hardware Root of Trust and Secure Boot (RoT), Side-Channel Attack Mitigation (SCA), and Trusted Execution Environments (TEE). Research questions: 1. What are the current state-of-the-art implementations of post-quantum cryptographic algorithms on resource-constrained embedded platforms (ARM Cortex-M, RISC-V)? 2. How have Physical Unclonable Functions evolved for IoT device authentication and key generation between 2020-2026? 3. What hardware root of trust and secure boot mechanisms have been developed or standardized for microcontroller-class devices? 4. What are the current countermeasures against side-channel and fault injection attacks on embedded processors, and what are their overhead costs? 5. How have Trusted Execution Environments been adapted for constrained devices, and what are the remaining deployment challenges? 6. How do these five security primitives integrate in practice, and what are the composition challenges? 2. INFORMATION SOURCES Four databases were systematically searched in February 2026, covering publications from January 2020 through January 2026: - IEEE Xplore (conference proceedings and journals): 847 records - IACR ePrint Archive and TCHES: 312 records - ACM Digital Library (including CCS, ASIA CCS, TECS): 523 records - arXiv cs.CR category: 418 records Total initial records: 2,100 3. SEARCH STRATEGY Primary search query: ("hardware security" OR "embedded security") AND ("microcontroller" OR "MCU" OR "IoT" OR "Cortex-M" OR "RISC-V") AND ("PQC" OR "post-quantum" OR "PUF" OR "secure boot" OR "side-channel" OR "TEE" OR "TrustZone") The query was adapted for each database's syntax while maintaining semantic equivalence. Domain-specific keywords supplemented the primary query: - PQC: CRYSTALS-Kyber, CRYSTALS-Dilithium, SPHINCS+, lattice-based - PUF: SRAM PUF, arbiter PUF, ring oscillator PUF - TEE: TrustZone-M, RISC-V PMP, Keystone - SCA: power analysis, electromagnetic side-channel, fault injection - RoT: secure boot, hardware security module, attestation 4. ELIGIBILITY CRITERIA Inclusion criteria (ALL must be met): 1. Published between January 2020 and January 2026 2. Addressed implementation on resource-constrained platforms: ARM Cortex-M series (M0, M0+, M3, M4, M7, M23, M33, M55, M85), RISC-V embedded cores (RV32I, RV32E, RV32IMC, RV64), or low-end FPGAs (