Computational Capabilities of the Trapped-Ion Quantum Computer

Trapped-ion quantum computer hardware is scaling to larger qubit numbers, but the computational capabilities of these devices remain largely unknown. From an abstract computer-science perspective, we address this problem in a two-step approach: First, we categorize levels of qubit connectivity for a processor based on ion-shuttling and individual ion addressing. Second, we apply computer-science techniques to develop optimized compilers that map arbitrary algorithms to sequences of ion-register reconfiguration and gate operations. We present compilers for 1D and 2D architectures, optimizing cost functions such as the qubit reconfiguration effort.