SiC-Based Half-Bridge Converter: Impact of Gate Resistance on Switching Behavior and Loss Estimation

This study explores the behavior of SiC MOSFETs in a half-bridge converter, emphasizing simulation and experimental validation under both ZVS and non-ZVS conditions. Fast switching and high efficiency make SiC attractive, but parasitic-induced oscillations and EMC require careful design. The influence of gate resistance on switching dynamics and loss mechanisms is analyzed, showing that higher gate resistance reduces oscillations but increases switching losses. For estimating the MOSFET dissipated power, traditional current sensing with current probes or shunt resistors introduces parasitic elements that affect the transistor switching and compromise the instantaneous power measurements. As a result, alternative methods were employed for loss estimation in high-frequency SiC converters. Results demonstrate that increasing gate resistance from 3 Ω to 30 Ω reduces oscillation amplitude by 41%, while increasing switching losses by 53.8%. These findings support gate-drive optimization in SiC-based converters.