Explainable Machine Learning Framework for RTL Timing Prediction: Bridging the Gap Between Black-Box AI and Hardware Design

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Authors: S. Eshwar Rao
Cited by: 0

Fields of Study & Subjects

Low-power high-performance VLSI design VLSI and FPGA Design Techniques Physical Unclonable Functions (PUFs) and Hardware Security

Publication details

Journal / source
Research Square
Publication date
6 January 2026
Document type
Preprint