A Novel Current Sensor Design for Enhanced IDDQ Testing in CMOS Circuits

This paper introduces a novel current sensor design aimed at improving IDDQ testing accuracy in modern low-power semiconductor technologies. Building on earlier measurement techniques, the proposed sensor distinguishes fault-induced currents from background leakage by analyzing their phase behavior under AC perturbation. The design enables enhanced fault discrimination while offering flexibility for integration either on-chip or off-chip. Analytical derivations and SPICE-based simulations, utilizing 0.8 ?m BICMOS technology, confirm the sensor?s capability to detect subtle current anomalies. These findings contribute to improved reliability in integrated circuit testing, particularly as device miniaturization amplifies leakage challenges.