A Novel Design of Energy Efficient CNTFET-Based Full Adder for VLSI Applications

Introduction: This paper presents the design and analysis of CNTFET-based full adders, demonstrating significant improvements in power efficiency, propagation delay, and circuit compactness compared to conventional CMOS designs. Materials and Methods: The proposed method leverages the superior electrical properties of CNTFETs to optimize arithmetic circuits for low-power and high-speed VLSI applications. Three different full-adder architectures (FA_C1, FA_C2, and FA_C3) are evaluated using the Cadence EDA Tool with a 32 nm CNTFET model. Simulation results confirm that among the proposed designs, FA_C3 achieves the best performance, exhibiting the lowest power consumption (0.0692 μW), the shortest propagation delay (6.791 ps), and minimal transistor count (12). Results: Compared to traditional CMOS-based adders, the proposed method achieves a 70% reduction in power consumption and a 33% improvement in speed, making it a viable solution for energyefficient ALUs, multipliers, and ripple carry adders. Discussion: The enhanced thermal stability, reduced power dissipation, and scalability of CNTFETbased adders position them as a promising alternative for next-generation portable electronics, IoT devices, and high-speed computing systems. Additionally, 16-bit, 32-bit, and 64-bit Ripple Carry Adders were implemented using the proposed full adder architectures. Conclusion: Among these, the FA_C3 design demonstrated superior performance in the 64-bit configuration, achieving a power consumption of 2.018 µW, a delay of 109.7 ps, and a power-delay product (PDP) of 221.5 aJ.