Efficient Architectures for LFSR Using State-Space Transformations

Background: Parallel designs for Linear Feedback Shift Registers (LFSRs) are used by Bose-Chaudhuri-Hocquenghem (BCH) encoders and Cyclic Redundancy Check (CRC). These LFSRs can be used for data transfer and reduce ATP (area-time product). Methods: In order to determine the number of XOR gates in transformation and companion matrices for generator polynomials of various CRC types, this research proposed a method. The suggested approach achieves a smaller area-time product in comparison to earlier architectures for XOR discovery. Despite having fewer Area-Time Products (ATPs), Delay Elements (Des), and XOR gates, CRC-32 has the same Critical Path Delay (CPD). A smaller area time product indicates a more effective implementation. Results: Accordingly, the total within-chip power seems to decrease sequentially with a variation of 3.99W, according to the experiment's results. The CRC-32 achieves 6% gate count reductions and 30% power savings. In digital system architecture, adding P-width pipeline stages is frequently used to reduce the data path and improve system performance. Discussion: This work describes a multi-bit parallel linear feedback shift register architecture using an XOR gate, a D flip-flop, and a transformation matrix. This technology significantly reduces power consumption without increasing (CPD) in comparison to previous techniques. Conclusion: In order to attain 32-bit LFSR functionality, 4-bit flip-flops minimize their clock route count, size, and power use. This technology significantly reduces power consumption without increasing Critical Path Delay (CPD) in comparison to previous techniques. Using simulations in the Vivado tool, the suggested design method has been verified and contrasted with conventional flip-flop implementation.