Reduction of digital filtering area in the residue number system based on truncated multiplication with accumulation blocks

Purpose of research. Parallel data processing based on the residue number system allows to reduce the hardware costs of digital signal filtering devices, which is one of the key problems of digital signal processing. Parallelization of calculations allowed to develop a method of digital signal filtering based on the use of truncated blocks of multiplication with accumulation in the residue number system. This article presents the advantages of using the developed approach and its limitations. Methods. The study used a method for organizing calculations in a system of residual classes with ranges of 32 and 48 bits and using balanced sets of modules of the form {2 − 1, 2 , 2 + 1}, an analytical assessment of the complexity of the device calculation, and hardware modeling in the Synopsys Design Compiler environment using the standard library. Results. The hardware cost reduction was recorded when using special modules {2 − 1, 2 , 2 + 1}, which allowed them to be reduced to 16,139.30 for 3-rd order filters, 31,152.99 for 7-th order filters, 62,507.06 for 15th order filters, and 126,564.46 for 31-st order filters with the organization of 32-bits arithmetic data processing in the residue number system. Thus, the hardware costs were reduced by 21.5%-23% relative to filters based on parallel-prefix adders using the Kogge-Stone method and by 20.6%-22.2% based on parallel carry adders with propagation. For 48-bit digital filters with arithmetic processing of data in the residue number system, the simulation results showed a reduction in hardware costs from 9.45% to 14% depending on their order. Conclusion. Carrying out calculations in the system of residual classes allows improving the operational characteristics of digital signal processing devices, for which the primary task is to minimize hardware costs.