A Review: O-ALU An Optimization-Enhanced Low Power ALU Design using Clock Gating and Power Gating

The rapid growth of portable, embedded, and IoT systems has made power efficiency a primary design constraint for Arithmetic Logic Units (ALUs), FPGA platforms, and RISC-V based processors. This review critically examines recent lowpower design techniques reported between 2020 and 2025, covering clock gating, data gating, power gating, architectural optimization, and emerging device-level solutions. The surveyed literature shows that clock- and activity-aware gating methods, such as hybrid clock gating and signal-based gating, can achieve dynamic power reductions in the range of 45–66% while maintaining acceptable performance. FPGA-based implementations further demonstrate that clock gating, pipelining, and bioinspired transition suppression can lower power consumption by up to 40%, though often at the cost of increased area and timing overhead. Technology-level innovations, including GDI logic, reversible logic, ternary logic, and sub-threshold operation, provide additional improvements in power-delay and energy-delay products, but their practical adoption is limited by design and verification complexity. At the system level, power-gated SRAM-FPGAs, FSM partitioning, and RISC-V based power management units enable substantial leakage and runtime power reduction, particularly for battery-constrained applications. Overall, the review indicates that hybrid strategies combining ALU-level gating, architectural power management, and systemlevel control offer the most balanced trade-off between power efficiency, performance, and scalability in modern digital systems.